A high-resolution stochastic time-to-digital converter with edge-interchange scheme

A high-resolution stochastic time-to-digital converter (STDC) using an edge-interchange scheme is described. The proposed STDC provides a higher resolution but consumes less power than previous STDCs that gave the same resolution. The limitation on input phase difference caused by the arbiter and the edge-interchange circuit is analyzed. Simulated results show that for the task proposed herein, a resolution of up to 0.3 ps is achieved while only 1.7mW is consumed. Furthermore, higher resolution is achieved, more power will be reduced by using the edge-interchange circuit.